Semiconductor embedded resistor generation

ABSTRACT

A method for generating an embedded resistor in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed substantially above the STI region.; etching the silicon layer to yield a polyconductor (PC) disposed substantially above the STI region; oxidizing the PC; depositing at least one of an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the at least one oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer disposed substantially above the STI region; patterning a transistor gate with a photo-resist mask disposed on another portion of the silicon layer disposed substantially away from the STI region; and etching the silicon layer to yield at least one transistor structure disposed substantially away from the STI region and at least one resistor structure disposed substantially above the STI region.

BACKGROUND OF THE INVENTION

The present disclosure generally relates to semiconductor integratedcircuits. More particularly, the present disclosure relates to thegeneration of embedded resistors in semiconductor integrated circuits.

Semiconductor integrated circuits may include various types of embeddedresistors. An OP type of resistor is formed by adding implants to apolyconductor (PC) or active region (RX) of an integrated circuit.Embedded resistors may include well types (e.g., N-Well), OP RX types(e.g., OP N+ Diffusion), and/or OP PC types (e.g., OP P+ PolySilicon).OP resistors are relatively inexpensive to generate because they useimplants and process parameters already in use for other components,such as transistors, in the semiconductor integrated circuits.

SUMMARY OF THE INVENTION

These and other issues are addressed by methods for generating embeddedresistors in semiconductor devices. Exemplary embodiments are provided.

An exemplary embodiment method for generating an embedded resistor in asemiconductor device includes forming a shallow trench isolation (STI)region in a substrate; forming a pad oxide on the STI region andsubstrate; depositing a silicon layer on the pad oxide; forming aphoto-resist mask on a portion of the silicon layer disposedsubstantially above the STI region; etching the silicon layer to yield apolyconductor (PC) disposed substantially above the STI region;oxidizing the PC; depositing at least one of an oxide material or ametal gate material on the oxidized surface; depositing a silicon layeron the at least one oxide material or metal gate material; depositingadditional silicon on a portion of the silicon layer disposedsubstantially above the STI region; patterning a transistor gate with aphoto-resist mask disposed on another portion of the silicon layerdisposed substantially away from the STI region; and etching the siliconlayer to yield at least one transistor structure disposed substantiallyaway from the STI region and at least one resistor structure disposedsubstantially above the STI region.

In a preferred embodiment, the silicon comprises polycrystalline silicon(Poly-Si), the oxide material comprises Hafnium Oxide (HfO2), and themetal gate material comprises Titanium Nitride (TiN). In an eFUSEembodiment, the method further includes forming a silicide portion on atleast one of the transistor or resistor structures. The step of forminga photo-resist mask on a portion of the silicon layer disposedsubstantially above the STI region is the only photo step added forforming a resistor structure. In a High-K Metal Gate (HKMG) embodiment,the step of depositing at least one of an oxide material or a metal gatematerial on the oxidized surface comprises depositing a High-K materialand a metal gate material. The High-K material may comprise at least oneof HfO2, AlO, ZrO2, TiO2, or like materials; and the metal gate materialmay comprise TiN, or like materials.

In a computer-readable storage medium embodiment, the program steps forgenerating an embedded resistor in a semiconductor device includeforming an STI region in a substrate; forming a pad oxide on the STIregion and substrate; depositing a silicon layer on the pad oxide;forming a photo-resist mask on a portion of the silicon layer disposedsubstantially above the STI region; etching the silicon layer to yield aPC disposed substantially above the STI region; oxidizing the PC;depositing at least one of an oxide material or a metal gate material onthe oxidized surface; depositing a silicon layer on the at least oneoxide material or metal gate material; depositing additional silicon ona portion of the silicon layer disposed substantially above the STIregion; patterning a transistor gate with a photo-resist mask disposedon another portion of the silicon layer disposed substantially away fromthe STI region; and etching the silicon layer to yield at least onetransistor structure disposed substantially away from the STI region andat least one resistor structure disposed substantially above the STIregion.

The present disclosure will be further understood from the followingdescription of exemplary embodiments, which is to be read in connectionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure provides methods for generating semiconductorembedded resistors in accordance with the following exemplary figures,in which:

FIG. 1 shows a schematic vertical side view of an OP polyconductor (PC)resistor structure;

FIG. 2 shows a schematic vertical side view of an OP PolycrystallineSilicon (Poly-Si) resistor structure;

FIG. 3 shows a schematic vertical side view of a High-K Metal Gate(HK/MG);

FIG. 4 shows a schematic vertical side view of an OP resistor structureafter shallow trench isolation (STI) formation in accordance with anexemplary embodiment of the present disclosure;

FIG. 5 shows a schematic vertical side view of an OP resistor structureafter pad oxidation and well ion-implantation (IIP) in accordance withan exemplary embodiment of the present disclosure;

FIG. 6 shows a schematic vertical side view of an OP resistor structureafter Poly-Si deposition in accordance with an exemplary embodiment ofthe present disclosure;

FIG. 7 shows a schematic vertical side view of an OP resistor structureafter OP PC resistor patterning in accordance with an exemplaryembodiment of the present disclosure;

FIG. 8 shows a schematic vertical side view of an OP resistor structureafter OP PC etch in accordance with an exemplary embodiment of thepresent disclosure;

FIG. 9 shows a schematic vertical side view of an OP resistor structureafter double-gate (DG) and extended-gate (EG) oxidation in accordancewith an exemplary embodiment of the present disclosure;

FIG. 10 shows a schematic vertical side view of an OP resistor structureafter Hafnium Oxide (HfO2) and Titanium Nitride (TiN) deposition inaccordance with an exemplary embodiment of the present disclosure;

FIG. 11 shows a schematic vertical side view of an OP resistor structureafter gate Poly-Si deposition in accordance with an exemplary embodimentof the present disclosure;

FIG. 12 shows a schematic vertical side view of an OP resistor structureafter gate patterning in accordance with an exemplary embodiment of thepresent disclosure;

FIG. 13 shows a schematic vertical side view of an OP resistor structureafter gate PC etching in accordance with an exemplary embodiment of thepresent disclosure;

FIG. 14 shows a schematic vertical side view of an OP resistor structureafter spacer formation in accordance with an exemplary embodiment of thepresent disclosure;

FIG. 15 shows a schematic vertical side view of an OP resistor finalstructure in accordance with an exemplary embodiment of the presentdisclosure;

FIG. 16 shows a schematic vertical side view of an eFUSE structure afterSTI formation in accordance with an exemplary embodiment of the presentdisclosure;

FIG. 17 shows a schematic vertical side view of an eFUSE structure afterpad oxidation and well IIP in accordance with an exemplary embodiment ofthe present disclosure;

FIG. 18 shows a schematic vertical side view of an eFUSE structure afterPoly-Si deposition in accordance with an exemplary embodiment of thepresent disclosure;

FIG. 19 shows a schematic vertical side view of an eFUSE structure aftereFUSE PC patterning in accordance with an exemplary embodiment of thepresent disclosure;

FIG. 20 shows a schematic vertical side view of an eFUSE structure aftereFUSE PC etching in accordance with an exemplary embodiment of thepresent disclosure;

FIG. 21 shows a schematic vertical side view of an eFUSE structure afterDG and EG oxidation in accordance with an exemplary embodiment of thepresent disclosure;

FIG. 22 shows a schematic vertical side view of an eFUSE structure afterHfO2 and TiN deposition in accordance with an exemplary embodiment ofthe present disclosure;

FIG. 23 shows a schematic vertical side view of an eFUSE structure afterGate Poly-Si deposition in accordance with an exemplary embodiment ofthe present disclosure;

FIG. 24 shows a schematic vertical side view of an eFUSE structure afterGate patterning in accordance with an exemplary embodiment of thepresent disclosure;

FIG. 25 shows a schematic vertical side view of an eFUSE structure afterGate PC etch in accordance with an exemplary embodiment of the presentdisclosure;

FIG. 26 shows a schematic vertical side view of an eFUSE structure afterSilicide and spacer formation in accordance with an exemplary embodimentof the present disclosure; and

FIG. 27 shows a schematic vertical side view of an eFUSE final structurein accordance with an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Exemplary methods are provided for generating semiconductor embeddedresistors. An OP type of resistor is formed by adding implants to apolyconductor (PC) or active region (RX) of an integrated circuit.Exemplary embodiment methods yield OP PC resistors, such as OP P+Polycrystalline Silicon (PolySilicon or Poly-Si) types, that areparticularly useful in bandgap reference circuits due to their negativetemperature coefficient characteristics. Method embodiments use fewerphotolithography steps for generating such resistors, and generallyreduce oxide damage versus prior methods.

Shallow trench isolation (STI) is a feature of integrated circuits thatacts to prevent electrical current leakage between adjacentsemiconductor device components. STI may be used with CMOS processtechnology nodes that are less than about 250 nanometers, for example.STI is created early during the semiconductor device fabricationprocess, before the resistors or transistors are formed. A typical STIprocess involves etching a pattern of trenches in the silicon,depositing one or more dielectric materials, such as silicon dioxide(SiO2), to fill the trenches, and removing the excess dielectric, suchas by planarization.

In exemplary OP PC resistors, the resistance decreases with increasingtemperature. Therefore, for PolySilicon resistor types, double-gate (DG)structures use a thicker oxide, extended-gate (EG) structures use amiddle-thickness oxide, and single-gate (SG) structures use a thinneroxide. For example, SG may be used for the core device while EG and DGmay be used for interfaces. OP P+ resistors are preferred for use inbandgap reference circuits due to their negative temperature coefficientcharacteristics.

As shown in FIG. 1, an OP polyconductor (PC) resistor is indicatedgenerally by the reference numeral 100. The resistor 100 includes asubstrate 110, a shallow trench isolation (STI) portion 112 disposed onthe substrate, a polyconductor (PC) portion 120 disposed on the STI, aside insulator 121 disposed on the STI around the PC, a spacer 136disposed on the STI around the side insulator, and a top insulator 140disposed over the substrate, STI, spacer, side insulator, and PCportions.

Turning to FIG. 2, a PolySilicon OP PC resistor is indicated generallyby the reference numeral 200. The resistor 200 includes a silicon (Si)substrate 210, a shallow trench isolation (STI) portion 212 disposed onthe substrate, a Poly-Si portion 230 disposed on the STI, a sideinsulator 231 disposed on the STI around the Poly-Si, a spacer 238disposed on the STI around the side insulator, and a top insulator 240disposed over the Si substrate, STI, spacer, side insulator, and Poly-Siportions.

Turning now to FIG. 3, a High-K Metal Gate (HK/MG) resistor is indicatedgenerally by the reference numeral 300. The resistor 300 includes asilicon (Si) substrate 310, an STI portion 312 disposed on thesubstrate, a (HfO2) portion 326 disposed on the STI, a (TiN) portiondisposed on the HfO2, a Poly-Si portion 330 disposed on the TiN, a sideinsulator 331 disposed on the STI around the Poly-Si, a spacer 338disposed on the STI around the side insulator, and a top insulator 340disposed over the Si substrate, STI, spacer, side insulator, and Poly-Siportions. Unfortunately, high resistance may prove hard to implement inthe HK/MG resistor 300 due to the low and non-linear resistancecharacteristics of the inserted metal layer 328.

As shown in FIG. 4, an exemplary embodiment OP resistor structure afterSTI formation is indicated generally by the reference numeral 400. Here,the structure 400 includes an elongated substrate 410, and an STIportion 412 disposed on the substrate substantially towards one end ofthe elongated substrate, leaving another end of the substrate withoutSTI disposed thereon. The STI formation process defines the isolationregion or portion.

Turning to FIG. 5, an exemplary embodiment OP resistor structure afterpad oxidation and well ion-implantation (IIP) is indicated generally bythe reference numeral 500. The structure 500 is similar to the structure400 of FIG. 4, so duplicate description may be omitted. Here, anoxidation layer 514 is disposed over the substrate 510 and STI 512. Thepad oxide is formed by an oxidation process, and channel IIP, such as VtTaylor, may be applied.

Turning now to FIG. 6, an exemplary embodiment OP resistor structureafter Poly-Si deposition is indicated generally by the reference numeral600. The structure 600 is similar to the structure 500 of FIG. 5, soduplicate description may be omitted. Here, a Poly-Si layer 616 isdisposed over the oxidation layer 614. The Poly-Si is deposited in orderto form an OP resistor and/or eFUSE. The Poly-Si thickness can bebetween about 0 Angstroms and about 2000 Angstroms, for example.

As shown in FIG. 7, an exemplary embodiment OP resistor structure afterOP PC resistor patterning is indicated generally by the referencenumeral 700. The structure 700 is similar to the structure 600 of FIG.6, so duplicate description may be omitted. Here, a photo-resist (PR)pattern 718 is disposed on the Poly-Si layer 716.

Turning to FIG. 8, an exemplary embodiment OP resistor structure afterOP PC etch is indicated generally by the reference numeral 800. Thestructure 800 is similar to the structure 700 of FIG. 7, so duplicatedescription may be omitted. After etching, a polyconductor (PC) 820portion of the former Poly-Si layer is disposed on the STI 812, and aresidual layer 822 is disposed over the remainder of the STI 812 andsubstrate 810.

Turning now to FIG. 9, an exemplary embodiment OP resistor structureafter double-gate (DG) and extended-gate (EG) oxidation is indicatedgenerally by the reference numeral 900. The structure 900 is similar tothe structure 800 of FIG. 8, so duplicate description may be omitted.Here, an EG oxide 922 is disposed over the exposed portion of the STI912 and the substrate 910, and a DG oxide 924 is disposed over the PC920.

In alternate embodiments, the oxidation process at this step can includesingle gate (SG) oxide, dual gate (DG) oxide, triple gate (TG) oxide,quadruple, and higher number of oxide processes. Thus, various oxidationprocesses may follow after poly patterning, and the present disclosureis not limited to DG, EG and SG, for example.

As shown in FIG. 10, an exemplary embodiment OP resistor structure afterHafnium Oxide (HfO2) and Titanium Nitride (TiN) deposition is indicatedgenerally by the reference numeral 1000. The structure 1000 is similarto the structure 900 of FIG. 9, so duplicate description may be omitted.Here, a Hafnium Oxide (HfO2) layer 1026 is disposed over the exposedportion of the STI 1012 and the substrate 1010, and over the DG oxide1024 on the PC 1020. In addition, a Titanium Nitride (TiN) layer 1028 isdisposed over the HfO2 layer. The thickness of the TiN 1028substantially above the PC 1020 and DG 1024 may be thinner than thethickness of the TiN elsewhere For example, the thickness of the TiN1028 substantially above the PC 1020, plus the thickness of the DG 1024above the PC 1020, may approximate the thickness of the TiN elsewhere.

In alternate embodiments, the high-K material may include HfO2, AlO,ZrO2, TiO2, and the like. In addition, oxide materials such as SiO2,SiON, DPN oxide, RPN oxide, and the like can also be used for gateoxide. Thus, the gate oxide is not limited to High-K. The metal gatematerial may be or include TiN or like materials.

Turning to FIG. 11, an exemplary embodiment OP resistor structure aftergate Poly-Si deposition is indicated generally by the reference numeral1100. The structure 1100 is similar to the structure 1000 of FIG. 10, soduplicate description may be omitted. Here, a level Poly-Si layer 1130is disposed over the TiN layer 1128, and a gate Poly-Si layer 1132 isdisposed on the Poly-Si 1130 substantially over the STI 1112. Thethickness of the level Poly-Si 1130 substantially above the PC 1120 maybe thinner than the thickness of the level Poly-Si elsewhere. Forexample, the thickness of the level Poly-Si 1130 that is substantiallyabove the PC 1120, plus the thickness of the gate Poly-Si 1132 above thePC 1120, may approximate the thickness of the level Poly-Si 1130elsewhere. Thus, the additional gate Poly-Si 1132 may be used to controlthe etch down to the PC 1120 while substantially preventing oxide damagethereon. Thus, additional Poly-Si may be deposited to form a High-Kmetal gate device.

Turning now to FIG. 12, an exemplary embodiment OP resistor structureafter gate patterning is indicated generally by the reference numeral1200. The structure 1200 is similar to the structure 1100 of FIG. 11, soduplicate description may be omitted. Here, a photo-resist (PR) mask1234 is disposed on the Poly-Si layer 1230 substantially towards the endof the elongated substrate without STI thereon.

As shown in FIG. 13, an exemplary embodiment OP resistor structure aftergate PC etching is indicated generally by the reference numeral 1300.The structure 1300 is similar to the structure 1200 of FIG. 12, soduplicate description may be omitted. After etching, the PC 1320 remainson the STI 1312, while a columnar stack of the HfO2 1326, TiN 1328 andPoly-Si 1330 remains on the substrate 1310.

Turning to FIG. 14, an exemplary embodiment OP resistor structure afterspacer formation is indicated generally by the reference numeral 1400.The structure 1400 is similar to the structure 1300 of FIG. 13, soduplicate description may be omitted. Here, a first spacer 1436 isdisposed on the STI 1412 around the PC 1420, and a second spacer 1438 isdisposed on the substrate 1410 around the columnar stack of the HfO21426, TiN 1428 and Poly-Si 1430.

Thus, patterning and formation of High-K metal gate devices may includeformation of lightly doped drains (LDD), spacers and deep source/drainstructures. A back-end-of-line (BEOL) process may be used, as may amiddle-of-line (MOL) process, including silicide formation. MOL stripand clean processes form the contacts to the resistors and transistorsafter implantation, before metallization layers are added. This includesselective removal of un-reacted metallic films after the formation ofself-aligned silicide on the source, drain and Poly-Silicon gateregions, as well as nitride spacer removal for optimization of strainenhancement and post contact-etch cleaning. BEOL strip and cleanprocesses involve cleaning after dielectric etching to form the canalsand vias that are later filled with diffusion barrier layers and metals.The cleaning step removes all etching and ash residue, including organicresidues, oxidized metallic residues and particulate contamination,without attacking the patterned metal lines or dielectric, or causingphysical damage to structures on the wafer surface.

Turning now to FIG. 15, an exemplary embodiment OP resistor finalstructure is indicated generally by the reference numeral 1500. Thestructure 1500 is similar to the structure 1400 of FIG. 14, so duplicatedescription may be omitted. Here, a leveling top insulator 1540 isdisposed over the substrate 1510, second spacer 1538, Poly-Si 1530,first spacer 1536 and PC 1520. Thus, the insulated PC 1520 with firstspacer 1536 forms an OP resistor. Simultaneously, the insulated columnarstack of Poly-Si 1530 disposed on TiN 1528, which is disposed on HfO21526, with second spacer 1538, forms a transistor.

As shown in FIG. 16, an exemplary embodiment eFUSE structure after STIformation is indicated generally by the reference numeral 1600. Here,the structure 1600 includes an elongated substrate 1610, and an STIportion 1612 disposed on the substrate substantially towards one end ofthe elongated substrate, leaving another end of the substrate withoutSTI disposed thereon.

Turning to FIG. 17, an exemplary embodiment eFUSE structure after padoxidation and well IIP is indicated generally by the reference numeral1700. The structure 1700 is similar to the structure 1600 of FIG. 16, soduplicate description may be omitted. Here, an oxidation layer 1714 isdisposed over the substrate 1710 and STI 1712.

Turning now to FIG. 18, an exemplary embodiment eFUSE structure afterPoly-Si deposition is indicated generally by the reference numeral 1800.The structure 1800 is similar to the structure 1700 of FIG. 17, soduplicate description may be omitted. Here, a Poly-Si layer 1816 isdisposed over the oxidation layer 1814.

As shown in FIG. 19, an exemplary embodiment eFUSE structure after eFUSEPC patterning is indicated generally by the reference numeral 1900. Thestructure 1900 is similar to the structure 1800 of FIG. 18, so duplicatedescription may be omitted. Here, a photo-resist (PR) pattern 1918 isdisposed on the Poly-Si layer 1916.

Turning to FIG. 20, an exemplary embodiment eFUSE structure after eFUSEPC etching is indicated generally by the reference numeral 2000. Thestructure 2000 is similar to the structure 1900 of FIG. 19, so duplicatedescription may be omitted. After etching, a polyconductor (PC) 2020portion of the former Poly-Si layer is disposed on the STI 2012, and aresidual layer 2022 is disposed over the remainder of the STI 2012 andsubstrate 2010.

Turning now to FIG. 21, an exemplary embodiment eFUSE structure after DGand EG oxidation is indicated generally by the reference numeral 2100.The structure 2100 is similar to the structure 2000 of FIG. 20, soduplicate description may be omitted. Here, an EG oxide 2122 is disposedover the exposed portion of the STI 2112 and the substrate 2110, and aDG oxide 2124 is disposed over the PC 2120.

As shown in FIG. 22, an exemplary embodiment eFUSE structure after HfO2and TiN deposition is indicated generally by the reference numeral 2200.The structure 2200 is similar to the structure 2100 of FIG. 21, soduplicate description may be omitted. Here, a Hafnium Oxide (HfO2) layer2226 is disposed over the exposed portion of the STI 2212 and thesubstrate 2210, and over the DG oxide 2224 on the PC 2220. In addition,a Titanium Nitride (TiN) layer 2228 is disposed over the HfO2 layer. Thethickness of the TiN 2228 substantially above the PC 2220 and DG 2224may be thinner than the thickness of the TiN elsewhere. For example, thethickness of the TiN 2228 substantially above the PC 2220, plus thethickness of the DG 2224 above the PC 2220, may approximate thethickness of the TiN elsewhere.

Turning to FIG. 23, an exemplary embodiment eFUSE structure after GatePoly-Si deposition is indicated generally by the reference numeral 2300.The structure 2300 is similar to the structure 2200 of FIG. 22, soduplicate description may be omitted. Here, a level Poly-Si layer 2330is disposed over the TiN layer 2328, and a gate Poly-Si layer 2332 isdisposed on the Poly-Si 2330 substantially over the STI 2312. Thethickness of the level Poly-Si 2330 substantially above the PC 2320 maybe thinner than the thickness of the level Poly-Si elsewhere. Forexample, the thickness of the level Poly-Si 2330 that is substantiallyabove the PC 2320, plus the thickness of the gate Poly-Si 2332 above thePC 2320, may approximate the thickness of the level Poly-Si 2330elsewhere. Thus, the additional gate Poly-Si 2332 may be used to controlthe etch down to the PC 2320 while substantially preventing oxide damagethereon.

Turning now to FIG. 24, an exemplary eFUSE structure after Gatepatterning is indicated generally by the reference numeral 2400. Thestructure 2400 is similar to the structure 2300 of FIG. 23, so duplicatedescription may be omitted. Here, a photo-resist (PR) mask 2434 isdisposed on the Poly-Si layer 2430 substantially towards the end of theelongated substrate without STI thereon.

As shown in FIG. 25, an exemplary embodiment eFUSE structure after GatePC etch is indicated generally by the reference numeral 2500. Thestructure 2500 is similar to the structure 2400 of FIG. 24, so duplicatedescription may be omitted. After etching, the PC 2520 remains on theSTI 2512, while a columnar stack of the HfO2 2526, TiN 2528 and Poly-Si2530 remains on the substrate 2510.

Turning to FIG. 26, an exemplary embodiment eFUSE structure afterSilicide and spacer formation is indicated generally by the referencenumeral 2600. The structure 2600 is similar to the structure 2500 ofFIG. 25, so duplicate description may be omitted. Here, a first silicide2637 is disposed on the PC 2620, and a second silicide 2639 is disposedon the Poly-Si 2630. A first spacer 2636 is disposed on the STI 2612around a columnar stack of the PC 2620 and the first silicide 2637, anda second spacer 2638 is disposed on the substrate 2610 around thecolumnar stack of the HfO2 2626, TiN 2628, Poly-Si 2630 and secondsilicide 2639.

Turning now to FIG. 27, an exemplary embodiment eFUSE final structure isindicated generally by the reference numeral 2700. The structure 2700 issimilar to the structure 2600 of FIG. 26, so duplicate description maybe omitted. Here, a leveling top insulator 2740 is disposed over thesubstrate 2710, second spacer 2738, second silicide 2739, first spacer2736 and first silicide 2737. Thus, the insulated first silicide 2737 onthe PC 2720 with first spacer 2736 forms an eFUSE. Simultaneously, theinsulated columnar stack of second silicide 2739, Poly-Si 2730, TiN2728, and HfO2 2726, with second spacer 2738, forms a transistor.

In method embodiments of the present disclosure, High-K and metal (e.g.,TiN) materials are removed naturally at the same time as the gateformation step. In addition, alternate embodiments are contemplated. Forexample, the resistance R of the resulting embedded resistors may beeasily adjusted by changing the thickness of the Poly-Silicon layers.Moreover, the Poly-Si itself may be replaced with comparable materials,such as single crystal silicon, or amorphous silicon (a-Si) with orwithout local crystallization.

Thus, method embodiments of the present disclosure may form an embeddedresistor using just one more photo step in addition to the steps alreadyperformed to form a transistor. In contrast, prior methods used at leasttwo additional steps; one for OP resistor patterning, and another tostrip away metal.

The use of eFUSEs permits dynamic real-time reprogramming of logicchips. For example, computer logic is etched onto a chip, and generallycannot be changed after the chip has been manufactured. By utilizingeFUSEs, the circuits on a chip may be changed while the chip is inoperation. Thus, eFUSEs may provide in-chip performance tuning. Forexample, if certain sub-systems fail, take too long to respond, orconsume too much power, the chip logic behavior can be instantly changedby intentionally blowing one or more eFUSEs. This process does notphysically destroy the eFUSE, so it is reversible and repeatable, suchas by using Joint Test Action Group (JTAG) programming. JTAG, or IEEEStandard 1149.1, is a standard that specifies how to control and monitorthe pins of compliant devices on a printed circuit board.

Although illustrative embodiments have been described herein withreference to the accompanying drawings, it is to be understood that thepresent disclosure is not limited to those precise embodiments, and thatvarious other changes and modifications may be effected therein by thoseof ordinary skill in the pertinent art without departing from the scopeor spirit of the present disclosure. such changes and modifications areintended to be included within the scope of the present disclosure asset forth in the appended claims.

1. A method for generating an embedded resistor in a semiconductordevice, the method comprising: forming a shallow trench isolation (STI)region in a substrate; forming a pad oxide on the STI region andsubstrate; depositing a silicon layer on the pad oxide; forming aphoto-resist mask on a portion of the silicon layer disposedsubstantially above the STI region; etching the silicon layer to yield apolyconductor (PC) disposed substantially above the STI region;oxidizing the PC; depositing at least one of an oxide material or ametal gate material on the oxidized surface; depositing a silicon layeron the at least one oxide material or metal gate material; depositingadditional silicon on a portion of the silicon layer disposedsubstantially above the STI region; patterning a transistor gate with aphoto-resist mask disposed on another portion of the silicon layerdisposed substantially away from the STI region; and etching the siliconlayer to yield at least one transistor structure disposed substantiallyaway from the STI region and at least one resistor structure disposedsubstantially above the STI region.
 2. The method of claim 1, furthercomprising forming a silicide portion on at least one of the transistoror resistor structures.
 3. The method of claim 2 wherein the at leastone of the transistor or resistor structures with silicide forms aneFUSE.
 4. The method of claim 1, further comprising forming at least onespacer around each of the transistor and resistor structures.
 5. Themethod of claim 4 wherein the at least one spacer is disposed directlyon the substrate.
 6. The method of claim 4 wherein the at least onespacer comprises an insulating material.
 7. The method of claim 1,further comprising forming an insulating layer above the transistor andresistor structures.
 8. The method of claim 1 wherein the step offorming a photo-resist mask on a portion of the silicon layer disposedsubstantially above the STI region is the only photo step added forforming a resistor structure.
 9. The method of claim 1 wherein the finalresistance of the resistor structure is adjusted by changing thicknessof a silicon layer.
 10. The method of claim 1 wherein an isolation areais defined by using the STI formation process.
 11. The method of claim1, further comprising performing well ion-implantation (IIP) in the samestep where the pad oxide is formed with oxidation.
 12. The method ofclaim 11 wherein the IIP is applied to a channel using a Vt Taylorprocess.
 13. The method of claim 1 wherein the silicon layer thicknessis between about 0 Angstroms and about 2000 Angstroms.
 14. The method ofclaim 1, further comprising planarizing the STI region and substrateprior to forming the pad oxide.
 15. The method of claim 1 whereinoxidizing the PC comprises at least one of processing with single-gate(SG) oxide, extended-gate (EG) oxide, dual-gate (DG) oxide, triple-gate(TG) oxide, quadruple or higher number of oxides.
 16. The method ofclaim 1 wherein depositing at least one of an oxide material or a metalgate material on the oxidized surface comprises depositing a High-Kmaterial and a metal gate material.
 17. The method of claim 16 whereinthe High-K material comprises at least one of HfO2, AIO, ZrO2, TiO2, orlike materials.
 18. The method of claim 1 wherein depositing at leastone of an oxide material or a metal gate material on the oxidizedsurface comprises depositing an oxide material and a metal gatematerial.
 19. The method of claim 18 wherein the oxide materialcomprises at least one of SiO2, SiON, DPN oxide, RPN oxide, or likematerials.
 20. The method of claim 1 wherein the metal gate materialcomprises TiN or like materials.
 21. The method of claim 1 wherein thesilicon comprises Polycrystalline Silicon (Poly-Si).
 22. A semiconductordevice, comprising: a substrate; a shallow trench isolation (STI) regiondisposed in the substrate; a pad oxide on the STI region; apolyconductor (PC) disposed substantially above the STI region; at leastone of an oxide material or a metal gate material on the PC; at leastone transistor structure disposed substantially away from the STIregion; and at least one resistor structure disposed substantially abovethe STI region.